M.Tech in Communication Engineering & Networks, NITK Surathkal (incoming) · B.Tech ECE, IIIT Nagpur. Architecting mission-critical RTL designs and high-performance digital systems.
National Institute of Technology Karnataka, Surathkal
Communication Engineering and Networks
Indian Institute of Information Technology Nagpur
Electronics and Communication Engineering · Grade: 7.5
Architecting Ethernet-based QSPI systems for JTAG-free remote bitstream updates.
Optimized RTL for symbol sync & AGC modules on Zynq-7000 with 15% faster convergence.
Top 2% (10 of 600 teams) in TrackShift 2025, hosted at Plaksha University with HAAS F1 support.
Bitmapper Technologies, Pune
National Remote Sensing Center (ISRO), Shadnagar
Vivado, Verilog, DRC/Timing/Power Reports
Automated synthesis & implementation report parser that flags critical violations, timing failures, and power/thermal issues before bitstream generation, tracing DRC and methodology violations back to exact RTL source.
SystemVerilog, Vivado, EDA Playground
FSM-based translator letting two identical-address devices coexist by remapping virtual addresses to a single physical device without affecting data integrity. Verified with a SystemVerilog testbench.
Designed and simulated a compact dual-band wearable antenna for ISM and Sub-6 GHz 5G NR applications, operating across 2.4442–2.5200 GHz and 3.6400–3.7652 GHz, using HFSS.
Real-time Syndrome-Based Error Correction Logic