Expertise in Verilog/SystemVerilog for complex digital system design and implementation on hardware.
Experience in developing and optimizing DSP algorithms for communications and error correction.
Skilled in the entire development pipeline, from system architecture on RFSOCs to application deployment.
National Remote Sensing Center, Shadnagar (ISRO)
May 2025 — Sept 2025
Contributing to mission-critical projects by developing and optimizing signal processing algorithms for satellite communication and remote sensing applications.
Arduino, Rectifiers, LoRaWAN, LCD
Engineered a self-sustaining sensor network achieving 3V output from ambient RF signals with a 10km+ transmission range.
Verilog, Vivado, BASYS3, ADS 2110 ADC
Designed a signal processing system for quadriplegic patients, reducing sensor interference by 30% using debouncing logic.
Status: Ongoing | Platform: HFSS
This research introduces a novel, compact, and flexible wearable antenna designed for ISM and 5G applications.
B.Tech in Electronics and Communication
Nov 2022 - Jul 2026 | Grade: 7.00
Senior Secondary
Jul 2020 - Aug 2022 | Grade: 96%
Digital Signal Processing
Embedded Systems
FPGA Development
Wireless Communications
Verilog, SystemVerilog
Python, C/C++
Vivado, TICS Pro, MATLAB
Proteus, ANSYS HFSS
Zynq-7000, UltraScale+ RFSOC
ADRV9361-Z7035 SDR
Arduino, Raspberry Pi
Linux, Windows
A demonstration of Forward Error Correction (FEC), a technique used to correct data corruption from noisy channels. This relates to my work with Reed-Solomon decoders.